|
Abstract |
3-4 |
|
摘要 |
4-7 |
|
CHAPTER 1: INTRODUCTION |
7-10 |
|
1.1 OBJECTIVES |
7 |
|
1.2 AUTHOR'S MAIN WORK |
7-8 |
|
1.3 ABOUT THIS ARTICLE |
8-10 |
|
CHAPTER 2: INTEGRATED ACCESS DEVICE |
10-21 |
|
2.1 BACKGROUND |
10-15 |
|
2.1.1 The Revolution of WAN |
10-11 |
|
2.1.2 The Flexibility Factor |
11-12 |
|
2.1.3 The Cost Factor |
12 |
|
2.1.4 The Intelligent Demarcation Point |
12-15 |
|
2.2 THE INTEGRATED ACCESS DEVICE |
15-17 |
|
2.3 CUSTOMER-SIDE INTERFACES |
17-18 |
|
2.4 NETWORK INTERFACES |
18-21 |
|
CHAPTER 3: INTEL IXP2350 NETWORK PROCESSOR |
21-37 |
|
3.1 INTEL NETWORK PROCESSOR ROADMAP |
21-22 |
|
3.2 IXP2350 OVERVIEW |
22-24 |
|
3.3 INTEL XSCALE CORE PROCESSOR |
24 |
|
3.4 MICROENGINES |
24-27 |
|
3.5 NETWORK PROCESSING ENGINES |
27-29 |
|
3.6 MEMORY SYSTEMS |
29-33 |
|
3.6.1 SRAM |
29-31 |
|
3.6.2 SDRAM |
31-33 |
|
3.7 MEDIA SWITCH FABRIC(MSF) |
33-34 |
|
3.8 SCRATCH PAD, HASH AND CAPs(SHAC) |
34-35 |
|
3.9 OTHER COMPONENTS |
35-37 |
|
3.9.1 Gig MAC Ethernet(GE) |
35-36 |
|
3.9.2 PCI Interface |
36-37 |
|
CHAPTER 4: DEVELOPMENT TOOL AND SOFTWARE ARCHITECTURE |
37-43 |
|
4.1 DEVELOPMENT TOOL |
37-40 |
|
4.1.1 Intel IXA SDK4.2 |
37-38 |
|
4.1.2 Developer Workbench |
38-39 |
|
4.1.3 Autopartitioning Programming Model |
39-40 |
|
4.3 INTEL EXCHANGE ARCHITECTURE |
40-43 |
|
4.3.1 Intel Exchange Architecture |
40-42 |
|
4.3.2 Microblock and Dispatch Loop |
42-43 |
|
CHAPTER 5: IXP2350 IAD HARDWARE OVERVIEW |
43-45 |
|
5.1 ASSUMPTION |
43 |
|
5.2 HARDWARE CONFIGURATION |
43-45 |
|
CHAPTER 6: DATA PLANE SOFTWARE IMPLEMENTATION |
45-69 |
|
6.1 PROJECT CONFIGURATION |
45 |
|
6.2 SOFTWARE OVERVIEW |
45-47 |
|
6.3 DISPATCH LOOP |
47-50 |
|
6.4 PACKET RX PPS |
50-54 |
|
6.4.1 Packet Rx Microblock |
50-53 |
|
6.4.2 Packet Rx PPS |
53-54 |
|
6.5 PACKET PROCESSING PPS |
54-60 |
|
6.5.1 Weighted Random Early Detection (WRED) Microblock |
54-55 |
|
6.5.2 Ethernet Decapsulation and Classify Microblock |
55-56 |
|
6.5.3 IPv4 Forwarder Microblock |
56-57 |
|
6.5.4 Packet Processing PPS |
57-60 |
|
6.6 TRAFFIC MANAGER PPS |
60-63 |
|
6.6.1 Qm DiffServ Scheduler Microblock |
60-61 |
|
6.6.2 Traffic Manager PPS |
61-63 |
|
6.7 FREELIST MANAGER PPS |
63-66 |
|
6.7.1 Freelist Manager Microblock |
63-64 |
|
6.7.2 Freelist Manager PPS |
64-66 |
|
6.8 PACKET TRANSMIT PPS |
66-69 |
|
6.8.1 Packet Transmit Microblock |
66-67 |
|
6.8.2 Packet Transmit PPS |
67-69 |
|
CHAPTER 7: CONTROL PLANE |
69-71 |
|
CHAPTER 8: PERFORMANCE |
71-74 |
|
CHAPTER 9: SUMMARIZE AND FUTURE WORK |
74-76 |
|
9.1 SUMMARIZE |
74 |
|
9.2 FUTURE WORK |
74-76 |
|
ACKNOWLEDGMENTS |
76-77 |
|
GLOSSARY |
77-80 |
|
个人简历及论文发表情况 |
80 |
